Shahin Nazarian, PhD
Senior Research Scientist in Electrical and Computer Engineering
Direct Dial: (626) 200-7893
Los Angeles Office
7958 Beverly Blvd
Los Angeles, CA 90048
Dr. Shahin Nazarian is an Associate Professor of Engineering Practice in the Department of Electrical Engineering at the University of Southern California. Prior to joining USC, he was a senior R&D software engineer in Magma Design Automation focusing on timing and noise solution development as part of Talus and Tekton tools. He has 8 years of industrial experience as a software and hardware design engineer in a wide range of areas, including computer-aided design and embedded system design. He has served as consultant to technical companies in various areas, such as VSLI design and verification, power management, operating systems, scheduling, and memory design. He is the first recipient of the USC Dean’s Award For Teaching Excellence (2014). He also received the USC Center For Excellence In Teaching Innovative undergraduate teaching award in 2011. He has served as an expert in both patent validity and infringement in licensing negotiations and litigation.
See more about Shahin’s: Qualifications | Areas of Expertise | Litigation Experience
Summary of Qualifications
- Has an accomplished career in both the semiconductor/electronics industry (eight years) and academia (seven years).
- Has specific experience in electronic design automation (EDA), a critical area of electrical engineering that crosses hardware/software boundaries.
- Has a deep understanding of integrated circuit (IC) and system-on-chip (SoC) design and verification.
- Has published original research in numerous prestigious conferences and scientific journals, such as the International Test Conference (ITC), the Design Automation Conference (DAC), and IEEE Transactions on Very Large Scale Integration Systems (TVSLI).
- Has taught more than ten different courses at the undergraduate and graduate levels in the areas of VLSI design, networks, architecture, logic design, embedded systems, system-on-chip, network-on-chip, and verification.
- Has served as the research advisor to scores of Masters and PhD students in the Electrical Engineering Department at USC.
- Has performed technical analysis of computer hardware intellectual property both in and outside of litigation.
Areas of Expertise
Digital, logic, VLSI circuits, Embedded, Custom, ASIC design, , Spec to gdsII, SoC, RTL, HDL Verilog, VHDL, SystemVerilog, SystemC, FPGA, synthesis, place and route, Cadence, Synopsys, Mentor Graphics, MATLAB, NoC
EDA/CAD tools and techniques
Behavioral synthesis, logic synthesis, static timing analysis, statistical timing analysis, statistical static timing analysis, power management, routing heuristics and algorithms, circuit optimization, C/C++, Tcl, simulation and optimization techniques
Emerging technologies, devices, circuits, and technologies MOS, CMOS, Nano-devices and wires, FinFETs, TFETs, smart grid, green computing, SPICE, HSPICE, MOS
Verification, validation and testing methodologies
UVM, OVM, VMM, coverage, prototyping, formal, symbolic, BIST, DFT, JTAG, Perl, Python, Tcl scripting, C/C++ reference model
Memories and controllers
DDRx SDRAMs, SRAMs, flashes, STTs, RRAMs, EPROM, Dynamic Ram Memory (DRAM), Flash Memory (NAND, NOR), EEPROM, HDD or SSD, E2PROM, EEPROM
Sockets, packet forwarding and routing, BGP, Distance Vector, NoC, Ethernet/802.3, token-ring/802.5
Cryptography, RSA, hashing
Multi-core, multi-threaded, GPU, microprocessors/controllers
Computer expert witness services, expert reports, testimony, intellectual property and patent infringement analysis, software and hardware design, source code inspection and review, breach-of-contract and non-performance claims.
Kinglite Holdings, Inc. v Giga-Byte Technology Co. Ltd et al.
July 2015 – Present
Jurisdiction: U.S. District Court for the Central District of California
Counsel: Stadheim & Grear
Nature of Suit: Patent